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debian for riscv open source hardware

User discussion about Debian Development, Debian Project News and Announcements. Not for support questions.
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tomazzi
Posts: 730
Joined: 2013-08-02 21:33

Re: debian for riscv open source hardware

#21 Post by tomazzi »

Thanks for the links - but this is not proving anythig: (the order of links is preserved)

1. Arty is only an FPGA-based CPU emulator.
2. SiFive avoids to say a word about the fact, that they are using an ARM Cortex M3 core (E300/U500)
3. ARM Cortex M3 core in an "free and open source HW"? (E300/U500) - just like the above.
4. Arrow is blocking all the TOR network, but they are stupid enough to advertise the #3 and #2 solutions as an "open HW", while they are not able to even provide correct HW specs: "Maximum Clock Rate (MHz): 0.032/12/25/166" - morons?

Links 2,3 and 4 are referring to a SmartFusion2 solution which have an integrated ARM Cortex M3 core.

hmm... this doesn't look promising...

Anyway, Regards.
Odi profanum vulgus

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pylkko
Posts: 1802
Joined: 2014-11-06 19:02

Re: debian for riscv open source hardware

#22 Post by pylkko »

My understanding is that the only people trying to implement RISC-V now are lowRISC and Sfive, and that the first lowRISC's will probably come without GPU as no open GPU exists. FPGA-emulation is apparently only good for development but the performance is significantly lower (not surprising, given emulation). Also in the news was the there is some "clean, RPM-built, bootable disk images" for Fedora on RISC-V

https://lists.fedoraproject.org/archive ... QZV4RJMQN/

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pylkko
Posts: 1802
Joined: 2014-11-06 19:02

Re: debian for riscv open source hardware

#23 Post by pylkko »

https://www.crowdsupply.com/sifive/hifive1
http://www.iotconnectivitysolutions.com/news/2016/11/29/8460023.htm wrote:announced the availability of its Freedom Everywhere 310 (FE310) system on a chip (SoC), the industry's first commercially available SoC based on the free and open RISC-V instruction set architecture, along with the corresponding low-cost HiFive1 software development board. As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for FE310 to the open-source community
On Extensions that are supported:
  • RV32I Base Integer Instruction Set, Version 2.0
  • “M” Standard Extension for Integer Multiplication and Division, Version 2.0
  • “A” Standard Extension for Atomic Instructions, Version 2.0
  • “C” Standard Extension for Compressed Instructions, Version 1.9
  • RISC-V Privileged ISA Specification, Version 1.9.1
  • RISC-V External Debug Support, Version 0.11

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