I have soldered the microcontroller onto a pcb with a groundplane on the bottom layer and the pic is on the top layer.
I'm using two 0.1µF ceramic bypass capacitors one for VDD & VSS and one for AVdd & AVss pair. I also have one 10kOhm pullup resistor on the MCLR pin. I have the programming header on the board just about 3cm away from the pic and couple of the first programming on this prototype board worked fine, but after these first programming runs ICD3 says the following:
Code: Select all
Programming...
program memory
Address: 0 Expected Value: 59 Received Value: 0
Failed to program device
Code: Select all
Connecting to MPLAB ICD 3...
Currently loaded firmware on ICD 3
Firmware Suite Version.....01.43.35
Firmware type..............PIC18F
Programmer to target power is enabled - VDD = 3,250000 volts.
Target device PIC18LF1220 found.
Device ID Revision = 7
The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x74f
configuration memory
Device Erased...
Programming...
program memory
Address: 0 Expected Value: 59 Received Value: 0
Failed to program device
Code: Select all
// CONFIG1H
#pragma config OSC = INTIO2 // Oscillator Selection bits (Internal RC oscillator, port function on RA6 and port function on RA7)
#pragma config FSCM = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
#pragma config IESO = ON // Internal External Switchover bit (Internal External Switchover mode enabled)
// CONFIG2L
#pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = OFF // Brown-out Reset Enable bit (Brown-out Reset enabled)
// BORV = No Setting
// CONFIG2H
#pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
// CONFIG3H
#pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled, RA5 input pin disabled)
// CONFIG4L
#pragma config STVR = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF // Low-Voltage ICSP Enable bit (Low-Voltage ICSP disabled)
// CONFIG5L
#pragma config CP0 = OFF // Code Protection bit (Block 0 (00200-0007FFh) code-protected)
#pragma config CP1 = OFF // Code Protection bit (Block 1 (000800-000FFFh) code-protected)
// CONFIG5H
#pragma config CPB = ON // Boot Block Code Protection bit (Boot Block (000000-0001FFh) code-protected)
#pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
// CONFIG6L
#pragma config WRT0 = OFF // Write Protection bit (Block 0 (00200-0007FFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection bit (Block 1 (000800-000FFFh) not write-protected)
// CONFIG6H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0001FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
// CONFIG7L
#pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (00200-0007FFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (000800-000FFFh) not protected from table reads executed in other blocks)
// CONFIG7H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0001FFh) not protected from table reads executed in other blocks)